Not applicable.
Not applicable.
This invention is in the field of wireless telephony, and is more specifically directed to audio output from multiple digital sources by way of a wireless telephone handset.
As is well-known in the art, digital modulation techniques have greatly improved the audio fidelity and transmission range of wireless telephones, while also significantly reducing the cost of service. Of course, the digital wireless telephone must demodulate and decode the incoming digital signal, and convert it into analog form to drive the audio speaker with a conventional audio signal. Accordingly, modem wireless telephones include a digital-to-analog converter (DAC) for performing this function.
A well-known DAC architecture is referred to as the oversampling xcexa3xcex94 (xe2x80x9csigma-deltaxe2x80x9d) DAC. A fundamental example of the oversampling xcexa3xcex94 DAC is described in Naus et al., xe2x80x9cA CMOS Stereo 16-bit D/A Converter for Digital Audio,xe2x80x9d Journal of Solid-State Circuits, VO. SC-22, No. 3 (IEEE, June 1987), pp. 390-395. According to this approach, the incoming digital data stream is oversampled by a significant multiple (e.g., 256 times the CD sample data rate of 44.1 kHz), and modulated into a one-bit data stream by a sigma-delta modulator. This one-bit data stream is applied to a 1-bit DAC that modulates a DC voltage with the one bit data stream to produce the output analog signal. In conventional DACs of this type, the sigma-delta modulator and the 1-bit DAC each operate at the oversampling clock frequency (e.g., 256 times the sample data rate, or about 11 MHz). This clock is conventionally generated by a phase-locked loop (PLL), based upon a system clock within the wireless telephone itself. As known in the art, phase locked-loop (PLL) circuits are used to generate stable clock signals at a fixed frequency relationship, generally a ratio of integers, relative to a reference clock. The frequency relationship is effected by a frequency divider applied to the reference clock and in the PLL feedback loop. In wireless telephones, the reference clock is typically the wireless clock frequency for the particular wireless transmission mode.
Modern advanced mobile computing devices and wireless telephone handsets are evolving from the so-called second generation (2G) technologies for wireless communications toward the capability of providing the so-called third generation (3G) wireless services. These 3G services are expected to extend current second generation voice and data services, and to include new very high bandwidth entertainment services including video and CD quality audio, interactive messaging including video and graphics, videoconferencing, video streaming, and remote control and monitoring services. These high-bandwidth services and applications of course place significant pressure on the wireless hardware, especially in receiving and outputting this multimedia content.
The digital signals from these various sources and transmission modes are at a wide range of data rates and frequencies. For example, digital audio tape (DAT) operates at a 48 kHz data rate, while compact disk (CD) audio is at a 44.1 kHz data rate. Other commonly encountered digital data rates include 32 kHz, 24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz. The advanced multi-purpose wireless telephone must therefore be able to perform digital-to-analog conversion of the incoming digital signals from each of these multiple signal sources, at each of these digital data rates, to provide a high-fidelity analog stereo audio output. However, the ability to convert data from any and all of these available data rates greatly complicates the architecture of the sigma-delta DAC.
By way of further explanation, FIG. 1 illustrates a conventional arrangement of a sigma-delta DAC using a PLL-based clock. Incoming baseband digital signal S, having a bandwidth fbw, is sampled by latch 4, which is clocked at an oversampling frequency fS applied by clock signal OSCLK from phase-locked loop (PLL) 2. Oversampling frequency fS is a frequency that is generally a large integral multiple of the signal bandwidth fbw. While the Nyquist criterion requires sampling of a signal at twice its bandwidth in order to accurately recover the signal, oversampling frequency fS is typically much greater than twice the bandwidth fbw. For example, a typical oversampling multiple is 256. In the case of a signal bandwidth fbw of about 40 kHz, the oversampling frequency fS is on the order of 10 MHz or higher.
PLL 2 is constructed in the conventional manner, and as such includes input frequency divider 10 for generating a reference clock signal based upon wireless clock WCLK. Frequency divider 10 presents the reference clock to one input of phase detector 12, which receives a feedback signal at its other input. Phase detector 12 produces an analog output signal based on the difference in phase between the reference clock and the feedback signal. This phase difference signal is filtered for stability by low-pass filter 14, and is applied to the control input of voltage controlled oscillator (VCO) 16. VCO 16 produces the output oversampling clock OSCLK, which is fed back through frequency divider 18 to the second input of phase detector 12. The oversampling clock OSCLK is thus locked to wireless clock WCLK, at a frequency multiple determined by the divisor ratio of frequency dividers 18, 10.
The oversampling clock OSCLK is applied to sampling latch 4, as noted above. Oversampling clock OSCLK also controls the modulation of sigma-delta modulator 6, which modulates the m bits of the sampled input signal S to a single-bit signal, in this example. 1-bit DAC 8, which is also clocked by oversampling clock OSCLK, receives the modulated output from modulator 6, and produces output analog signal s(t).
While the arrangement of FIG. 1 is well suited for generating an oversampling clock OSCLK at a reasonable multiple of wireless clock WCLK, this task becomes exceedingly difficult if signals of varying frequency are to be processed by this circuit. This is because there is no small set of integers that can be used in PLL 2 to produce the desired oversampling clock OSCLK at all of the necessary audio standard frequencies.
In addition to the differences in data rates of the various signal sources, multiple broadband communications standards are now in place. Indeed, the 3G communications standard itself (xe2x80x9cIMT-2000xe2x80x9d) defines a family of radio interfaces that are suitable for a wide range of environments. Furthermore, some wireless communications standards are extensions of 2G modulation techniques, extending the data rates of 2G standards toward the levels required for 3G communications. To further complicate this field, different regions of the world have gravitated toward different wireless communications technologies. Unfortunately, these various standards operate at different clock rates. For example, the wireless clock (WCLK in FIG. 1) for EDGE transmission is 26 MHz, the GSM clock is 13 MHz, the WCDMA clock is at 15.36 MHz, D-AMPS operates at 19.44 MHz, PDC operates at one of 12.6/12.8/14.4/16.8 MHz, PHS at 16.8 or 8.4 MHz, and AMPS operates at 14.4/15.36/16.8 MHz.
Because of the varying incoming signal sample rates and the wide number of possible wireless transmission modes, a set of ratios of relatively small integers of the various wireless- clock frequencies cannot be derived, for use in a conventional PLL, to produce the wide range of oversampling clock frequencies necessary for D/A conversion in all combinations.
By way of further background, another type of known oversampled DAC does not require the generation of clock frequencies at an exact multiple of the input sample rate. An example of a DAC of this type is illustrated in FIG. 2, in which digital signal S is sampled by latch 4, oversampled by latch 5, modulated by sigma-delta modulator 6, and converted into the analog domain by DAC 8. Latch 5, modulator 6, and DAC 8 are clocked by oversampling clock OSCLK, which is at a frequency based on wireless clock WCLK. This oversampling clock signal OSCLK is divided down from wireless clock WCLK by frequency divider 20 so that the design of DAC 8 and other circuitry may be kept relatively modest. For example, if wireless clock WCLK is at a frequency of 13 MHz, oversampling clock OSCLK may be divided down from wireless clock WCLK by a factor of five, so that DAC 8 and the other circuitry can operate at the more modest frequency of 2.6 MHz.
Sampling latch 4 is controlled by clock SCLK, which is generated by frequency divider 24 under the control of state machine 22. Dual frequency divider 24 divides oversampling clock OSCLK by either integer divisor M or by the next incremental integer divisor M+1, depending upon a control signal issued by state machine 22. Alternatively, dual divider 24 may receive wireless clock WCLK at its input, and divide its frequency down directly. According to this construction, state machine 22 controls the number of times that dual divider 24 divides the frequency of its incoming clock by the integers M, M+1 so that, on the average, sample clock SCLK has a frequency that is a desired oversampling multiple of the Nyquist frequency 2 fbw. For example, if wireless clock WCLK has a frequency of 13 MHz and frequency divider 20 divides this clock signal down by a factor of five to producing oversampling clock OSCLK at 2.6 MHz, and if input signal S has a bandwidth of 22.05 kHz and thus a sample rate of 44.1 kHz, sampling clock SCLK at an average frequency of 44.1 kHz can be generated by dividing oversampling clock OSCLK by a ratio of 26000/441, which is expressed in simplest terms. While these integers are too large to be reasonably implemented in a PLL, this frequency division is accomplished in the conventional circuit of FIG. 2 by state machine 22 controlling frequency divider 24 to divide oversampling clock OSCLK by a factor of 59 (M30) approximately 96% of the time, and by a factor of 58 (M) approximately 4% of the time. Over time, the average frequency of sampling clock SCLK approaches 44.1 kHz, which is the audio sample rate of signal S.
Latch 5 then oversamples the sampled output of latch 4, at the higher oversampling rate of oversampling clock OSCLK itself. In the example given above, latch 5 will sample 96% of the samples taken by latch 4 59 times, and will sample 4% of these samples 58 times. The oversampled output is then applied to modulator 6 and DAC 8, which provide the analog output under the control of the oversampling clock OSCLK.
While the approach of FIG. 2 is able to oversample an input signal of arbitrary frequency at any desired ratio, on the average, the unavoidable jitter between the M and M+1 samples of the input signal produces spurious signals in the audio band. This audio noise undesirably affects the output analog signal. In addition, even with frequency division applied by frequency divider 20, 1 bit DAC 8 must be designed to operate at a relatively highfrequency, which involves substantial design constraints and significant power dissipation.
According to another known approach, an example of which is shown in FIG. 3, the extent of the spurious noise can be minimized by increasing the number of samples per input sample, so that relative time differences between the M and M+1 samples are minimized. As described in Kwan et al., xe2x80x9cA Stereo Multibit xcexa3xcex94 DAC with Asynchronous Master-Clock Interfacexe2x80x9d, Journal of Solid-State Circuits, Vol. 31, No. 12 (IEEE, December 1996), pp. 1881-1887, audio noise due to jitter in the oversampling is reduced by driving the DAC with a low-jitter clock that is independent from the PLL clock used to oversample and interpolate the input signal.
In the example of FIG. 3, a very high frequency clock signal FCLK, for example on the order of 50 MHz, is received at the input of dual divider 28. As in the previous examples, dual divider 28 is controlled by sigma-delta modulator 26 to divide down clock signal FCLK by integers M, M+1, and generate a resampling clock ACLK. According to this circuit, the desired frequency of resampling clock ACLK is, on the average, equal to that of the sample rate of incoming signal S; accordingly, the relative fractions of the cycles that are divided by integers M and M+1 are controlled, by sigma-delta modulator 26, to produce this average frequency. As a result, a sample rate of the input signal is twice the bandwidth of the signal (2 fbw) is related to the frequency fF by:       2    ⁢          f      bw        =            f      F              M      ⁢              (                  1          +          α                )            
where xcex1 is the relative fraction of the samples that are oversampled at the frequency of FCLK divided by M+1. Because the frequency of very high frequency clock FCLK is much higher than that of the wireless and oversampling clocks in the previous conventional circuits, the spurious noise in the audio band is greatly reduced in the circuit of FIG. 3. For example, for very high frequency clock FCLK at a frequency of on the order of 50 MHz, the audio noise is very low for input signal S at the CD rate of 44.11 kHz. This of course requires relatively large divisor values M, M+1, for example 1133 and 1134, respectively, for FCLK at 50 MHz.
Resampling clock ACLK, at an average frequency equal to the input sample rate (e.g., 44.1 kHz), is applied to the clock input of latch 4, which samples signal S and applies the sample values to the input of oversampling latch 32. Oversampling latch 32 is clocked by very high frequency clock signal FCLK, and oversamples the sampled output of latch 4. As noted above for the values of M, M+1, the oversampling performed by latch 32 provides a large number of oversample values for each sample of the input signal (i.e., 1133 or 1134). The oversampled output of latch 32 is then filtered by digital filter 34, which is a conventional sinc (sinx/x) filter for eliminating power at the multiples of the frequency at which D/A conversion is performed downstream, in the conventional manner. Decimating filter 36 then decimates the filtered oversampled sequence, in the conventional manner, by a multiple K with which clock DACLK is divided down from very high frequency clock FCLK. The decimated digital datastream is then applied to second sampling latch 37, which samples the decimated filtered oversampled signal, at clock rate DACLK which is divided down from very high frequency clock FCLK by a factor K, performed by frequency divider 20. The samples from switch 37 are then applied to sigma-delta modulator 6, and in turn to 1-bit DAC 8, as before. In this example of FIG. 3, latch 4, modulator 6, and DAC 8 are all clocked by a relatively high speed clock DACLK, which is at a frequency divided down from clock FCLK to on the order of 3 MHz or so by frequency divider 20. DAC 8 then outputs the analog signal s(t).
As noted above, the noise performance of the circuit of FIG. 3 is quite good, considering that the difference in the number of samples is quite small when the oversampling multiple is as large as one thousand or greater, as in this example. However, the circuit of FIG. 3 requires the generation and use of an extremely high frequency clock FCLK, for example on the order of 50 MHz. The clock circuitry for generating this clock, and the circuits utilizing this clock (divider 28, oversampling latch 34, filters 34, 36, etc.), are necessarily more complex when operating at such high frequencies. In addition, the power dissipated also increases with increasing operating frequency, which is of great concern in battery-powered systems such as wireless telephones. Accordingly, the solution provided by the circuit of FIG. 3 is somewhat unattractive even if the very high frequency clock FCLK is available, which in many systems it is not.
It is therefore an object of this invention to provide a digital-to-audio converter that provides high fidelity oversampling of the input digital data stream without actually generating and using high frequency clock signals.
It is a further object of this invention to provide such a converter that is capable of converting digital data at one of a multiple of sample frequencies.
It is a further object of this invention to provide such a converter in which a wide range of wireless clocks may be used in the conversion.
It is a further object of this invention to provide such a converter that is suitable for digital implementation in a battery-powered device such as a wireless telephone.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented into an audio circuit for converting a digital baseband signal into an analog output. The circuit includes a first sigma-delta circuit that controls a dual frequency divider. The dual divider divides a system clock, such as in a wireless telephone, by successive integers, under the control of a first sigma-delta circuit. An output clock is generated by the dual divider to sample the incoming baseband signal at near its Nyquist frequency. The output of the dual divider is also applied, as a clock, to a second sigma-delta circuit that determines the number of oversamples to be associated with each baseband sample. This number of samples and the Nyquist-sampled baseband signal are applied to a digital filter. The digital filter synthesizes a filtered version of an oversampled output signal based on these inputs, and the synthesized output signal is converted to analog.